Technical Field
The disclosure relates to a clock and data recovery circuit, and more particularly, to a clock and data recovery circuit module, a memory storage device and a phase lock method.
Description of Related Art
Generally, in a signal transmission system, a transmitter uses its clock to generate a data signal and then transmits said data signal to a receiver. As for the receiver, in order to correctly identify a logical level of the data signal, the receiver must read the data signal according to a clock that is synchronous with the clock of the transmitter. Therefore, the receiver often uses a clock and data recovery (CDR) circuit module to recover the clock of the transmitter.
In some specific cases, the receiver may detect a frequency of the data signal and sample a reference clock according to the detected frequency, so as to perform a phase lock that is relatively more accurate. However, sampling the reference clock by using the frequency of the data signal may result in larger system power consumption and a design cost may also be increased accordingly since a circuitry with high circuit complexity is required to process a sampling result.
Nothing herein should be construed as an admission of knowledge in the prior art of any portion of the present disclosure. Furthermore, citation or identification of any document in this application is not an admission that such document is available as prior art to the present disclosure, or that any reference forms a part of the common general knowledge in the art.